@article{
    DubJunHel:SCP-AVOCS,
    author = "Dubrovin, Jori and Junttila, Tommi and Heljanko, Keijo",
    volume = "77",
    issn = "0167-6423",
    optcountry = "Netherlands?",
    language = "eng",
    title = "Exploiting step semantics for efficient bounded model checking of asynchronous systems",
    url = "http://dx.doi.org/10.1016/j.scico.2011.07.005",
    journal = "Science of Computer Programming",
    publisher = "Elsevier",
    doi = "10.1016/j.scico.2011.07.005",
    number = "10--11",
    abstract = "This paper discusses bounded model checking (BMC) for asynchronous systems. Bounded model checking is a technique that employs the power of efficient SAT and SMT solvers for model checking. The main contribution of this paper is the presentation of a simple modeling formalism independent way of translating an asynchronous system into a transition formula for three partial order semantics: the exists-step semantics, its generalization, the relaxed exists-step semantics, and a novel variant that combines the latter with the idea of process semantics. Step and process semantics have been introduced in earlier works for different low level asynchronous system formalisms to improve the efficiency of BMC. However, this paper is the first one showing how to translate the semantics for any asynchronous system modeling formalism including high-level data manipulation operations while encoding the independence of actions in a dynamic fashion. Thus, the approaches have been extended to cover a larger class of modeling formalisms. The technical approach uses the notion of a coherent encoding of the transition relation, making for a simple and elegant translation of the partial order semantics in question. The presented translations have been implemented and we present extensive empirical results comparing the efficiency of the different translations to each other as well as as to an explicit state model checker DiVinE on its own BEEM benchmark suite.",
    responsibleauthor = "Dubrovin, Jori and Junttila, Tommi and Heljanko, Keijo",
    corerank = "A",
    juforank = "2",
    il = "no",
    year = "2012",
    keywords = "bounded model checking, step encodings, process semantics, asynchronous systems, SMT",
    unitcode = "T306-99, T312-1",
    impactfactor = "A1",
    pages = "1095--1121",
    flags = "public DC logic"
}